1. Field of the Invention
The present invention relates to a mask pattern. In particular, the present invention relates to a pattern forming method and system, which are suitable for forming patterns having a sufficient process margin, and to a method of manufacturing a semiconductor device using the pattern forming method.
2. Description of the Related Art
Recently, high integration and high-speed performance of semiconductor devices have advanced. For this reason, the requirements for pattern formation of semiconductor integrated circuits are very severe.
In semiconductor integrated circuits, the design rule representing the design and manufacture minimum line width becomes narrow with the improvement of nano-fabrication techniques. At present, semiconductor integrated circuits having a line width of less than 100 nm are manufactured.
If a range satisfying the foregoing design rule is given, designers can freely make a design of the circuit pattern.
Semiconductor integrated circuits are manufactured by etching various material films formed on a semiconductor substrate using resist patterns formed by a lithography technique as masks. For this reason, predetermined rule (pattern rule) is required in the pattern critical dimensions of each exposure mask and relative pattern critical dimensions between exposure masks.
For example, when the layout of the semiconductor integrated circuits is designed, the following matters are determined as the pattern arrangement rule. One is the minimum processing dimension, and another is dimension change (difference in processing conversion) before and after processing. Another is alignment accuracy when overlapping different exposure masks.
However, the circuit pattern is micronized, thereby influencing the semiconductor device characteristic resulting from the following reason. The pattern formed on the exposure mask is transferred onto the semiconductor substrate in the lithography process in the manufacture of semiconductor devices. In this case, deviation is given due to optical proximity effect (OPE) between design dimension and actual dimension when transferred onto the semiconductor substrate.
For example, even if the pattern satisfies the design rule, the acute portion of the pattern is not fully transferred; as a result, it becomes round. In addition, line dimension changes due to isolated and nested distribution of the line pattern.
In order to correct the deviation, the following method, that is, the optical proximity correction (OPC) technique, has been known. According to the OPC technique, the pattern critical dimensions on the exposure mask are corrected using optical simulation. For example, the pattern width is partially thickened, or a dummy pattern is provided.
However, the OPC technique corrects the pattern critical dimensions on the exposure mask so that the pattern formed on the semiconductor substrate is formed as design pattern critical dimensions. Thus, the OPC technique is not suitable for increasing the process margin in the lithography process.
Consequently, the OPC technique is not effective with respect to a patterns having process margin, which does not satisfy the reference value. The process margin shows an allowable range where the pattern is formed based on the dimensions having no problem on the semiconductor device characteristic even if the following condition is given. The condition is that exposure parameters, for example, exposure and focal length vary from their proper value when the pattern is transferred onto the semiconductor substrate.
The pattern forming method to solve the foregoing problem is disclosed in JPN. PAT. APPLN. KOKAI Publication No. 2002-131882 (pages 5 to 8, FIG. 2), for example.
The pattern forming method disclosed in the Publication No. 2002-131882 will be explained with reference to FIG. 17 to FIG. 20. FIG. 17 is a flowchart to explain the pattern forming method. FIG. 18 is a view showing the layout before circuit patterns are corrected. FIG. 19 is a layout view showing circuit the patterns of maximum and minimum line dimension when conditions such as an exposure amount and a focal length are varied to the circuit patterns shown in FIG. 18. FIG. 20 a view showing the layout after the circuit patterns shown in FIG. 18 are corrected.
As shown in FIG. 18 to FIG. 20, the pattern is composed of lines and spaces. More specifically, patterns 102 to 104 are arranged in parallel on an exposure mask 101. The pattern 102 has a line dimension L1. The pattern 103 has a line dimension L2, and is formed via a space dimension S1. The pattern 104 has a line dimension L3, and is formed via a space dimension S2.
First, the design pattern data is read from a data recorder, and a process margin is obtained from the relation between lines and spaces. Thereafter, the pattern having process margin, which does not satisfy the reference value, is extracted from the design pattern.
More specifically, lithography simulation is carried out while changing the exposure and focal length by predetermined ratio. By doing so, variables δ1 to δ3 of line dimensions L1 to L3 of patterns 102 to 104 are determined.
In the foregoing Publication No. 2002-131882, it is determined that δ2 and δ3 are larger than δ1, and each process margin of patterns 103 and 104 does not satisfy the reference value (step S101).
The pattern is corrected so that the process margin satisfies the reference value (step S102). More specifically, both edges 103a and 103b of the pattern 103 are shifted to their sides so that the line dimension L2 is widened to L2′. An edge 104a of the pattern 104 is shifted to the side so that the line dimension L3 is widened to L3′.
The pattern is corrected, and thereafter, a check is made whether or not the pattern pitch is kept constant (step S103).
If the pattern pitch is not kept constant, the procedure returns to step S102, and then, the pattern is again corrected in the following manner. Space dimensions S1 and S2 are narrowed down to S1′ and S2′ in accordance with the line dimension correction so that the pattern pitch before and after correction is kept constant.
Then, it is determined whether or not the wiring capacitance of the corrected pattern is in an allowable range (step S104). This is because the following matter is taken into consideration. In correcting the process margin of the pattern, the line dimension is widened, and thereby, there is a possibility described below. Parasitic capacitance (wiring capacitance) generated between top and bottom layers exceeds an allowable value in multi-layer interconnection.
If the wiring capacitance is not in the allowable range, the procedure returns to step S102, and then, the pattern is again corrected.
If the wiring capacitance is in the allowable range, it is determined whether or not the corrected pattern satisfies the design rule. More specifically, it is determined whether or not the line and space dimensions of the corrected pattern are more than the minimum line and space dimensions predetermined in the design rule (step S105).
If the corrected pattern does not satisfy the design rule, the procedure returns to step S102, and then, the pattern is again corrected to satisfy the design rule.
On the other hand, if the corrected pattern satisfies the design rule, the optical proximity correction (OPC) is carried out with respect to the necessary portions of the corrected pattern (step S106).
Finally, an exposure mask is prepared based on the corrected design pattern data (step S107).
The Publication No. 2002-131882 discloses the method of another embodiment taking the relation of one contact hole pattern with the space between adjacent contact hole patterns. According to the method of another embodiment, a pattern having a process margin, which does not satisfy the reference value is extracted. Thereafter, the extracted pattern is corrected to satisfy the process margin.
As described above, the pattern forming method disclosed in the Publication No. 2002-131882 improves the process margin of the following patterns. The patterns are patterns (line patterns) to be formed on the same exposure mask or patterns in the same exposure mask such as a contact hole pattern.
However, higher accuracy is required in pattern transfer to the semiconductor substrate, and in addition, further technical development is required to manufacture high-integrated semiconductor devices.
The foregoing pattern forming methods have a problem that it is not suitable for improving the process margin between patterns to be formed using a plurality of exposure masks.